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fujitsu semiconductor fr50 32-bit microcontroller MB91F367Ga/f368ga datasheet release 1.0 10-apr-2001
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 2 10-apr-01 revision histor y revision date item 1.0 10-apr-2001 first revision of preliminary datasheet for MB91F367Ga and mb91f368ga
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 3 10-apr-01 table of contents 1 MB91F367Ga/f368ga overview . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MB91F367Ga block structure . . . . . . . . . . . . . . . . . . . . . . 6 1.2 mb91f368ga block structure . . . . . . . . . . . . . . . . . . . . . . 7 1.3 core functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 pin assignment MB91F367Ga . . . . . . . . . . . . . . . . . . . . . 14 1.6 pin assignment mb91f368ga . . . . . . . . . . . . . . . . . . . . . 15 1.7 i/o pins and their functions . . . . . . . . . . . . . . . . . . . . . . . 16 1.8 flash memory mode of MB91F367Ga/f368ga . . . . . . . 20 2 additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1 flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.1 flash control status register (fmcs) . . . . . . . . . . . . . . . 22 2.1.2 flash wait control register (fmwt) . . . . . . . . . . . . . . . 23 2.2 f362 mode register (f362md) . . . . . . . . . . . . . . . . . . . . . 27 2.3 oscillation stabilization time . . . . . . . . . . . . . . . . . . . . . . . 28 2.4 subclock rtc32 (clkr2) . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 io-map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 power-on-sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 handling of unused input pins . . . . . . . . . . . . . . . . . . . . . . . . 30 7 emulation device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 run mode current/power consumption . . . . . . . . . . . . . . . 36 9.3.1 logic power consumption . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.2 analog power consumption . . . . . . . . . . . . . . . . . . . . . . 37 9.3.3 i/o and smc power consumption . . . . . . . . . . . . . . . . . . 37 9.4 converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.5 clock settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6 clock modulator settings . . . . . . . . . . . . . . . . . . . . . . . . . . 40 appendix a i/o map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 appendix b interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 4 10-apr-01
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 5 10-apr-01 chapter 1 MB91F367Ga/f368ga overview this device is available in two options. the difference between these options is as follows: see the followin g chapters for more details: feature MB91F367Ga mb91f368ga rtc module connected to 4 mhz oscillator connected to 32khz oscillator at pins 27, 28 calibration unit available
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 6 10-apr-01 1.1 MB91F367Ga block structure user ram 16 kb bit search module boot rom 2kb dma controller fr50 core watchdog timer instruction ram 4kb bus converter r-bus adapter user logic bus interface can (2ch) sio prescaler/ sio (2ch) u-timer/ uart (1ch) rtc i 2 c adc (8 ch) external interrupt (8 ch) prog. pulse generator (4ch) icu (4 ch) ocu (2 ch) free running counter (2 ch) 32 32 32 16 32 voltage regulator 4 mhz oscillator clock modulator power down reset reload timer (3ch) alarm comparator f-bus ram 16 kb flash memory 512 kb
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 7 10-apr-01 1.2 mb91f368ga block structure user ram 16 kb bit search module boot rom 2kb dma controller fr50 core watchdog timer instruction ram 4kb bus converter r-bus adapter user logic bus interface can (2ch) sio prescaler/ sio (2ch) u-timer/ uart (1ch) rtc i 2 c adc (8 ch) external interrupt (8 ch) prog. pulse generator (4ch) icu (4 ch) ocu (2 ch) free running counter (2 ch) 32 32 32 16 32 voltage regulator 4 mhz oscillator clock modulator power down reset reload timer (3ch) alarm comparator f-bus ram 16 kb flash memory 512 kb 32khz subclock calibration unit
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 8 10-apr-01 1.3 core functionality function feature remarks fr50 core 32-bit fujitsu risc core fr30 software compatible clock module (clock control, clock divider, plls) setting of frequencies for cpu and peripherals (see mb91fv360ga) low power consumption modes: rtc mode : only the r eal t ime c lock and the selected oscillator are active (= stop mode and bit 0 of stcr is set to 0) stop mode : all internal circuits and the oscillation circuits are halted watchdog adjustable watchdog timer interval (between 2 20 and 2 26 system clock cycles) i-ram 4 kb i-ram see remark below table d-bus ram 16 kb ram for user data see remark below table f-bus ram 16 kb ram for data and code see remark below table flash memory 512 kb sector architecture: sector 0: 64 kb | sector 7: 64 kb sector 1: 64 kb | sector 8: 64 kb sector 2: 64 kb | sector 9: 64 kb sector 3: 32 kb | sector 10: 32 kb sector 4: 8 kb | sector 11: 8 kb sector 5: 8 kb | sector 12: 8 kb sector 6: 16 kb | sector 13: 16 kb | | v v 16 bit 16 bit write access is 16 bit wide, read access can be 16 or 32 bit wide connected to f-bus minimum 10000 program/erase cycles minimum 10 years data retention net read cycle time to the memory is 40ns. for overall access time see settings in chapter 2.1 boot rom 2 kb dma 5 channels up to 16 dma sources can be used transfer modes: single/block, burst, continuous
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 9 10-apr-01 remark: set bit 9 ( syncr ) of tbcr to 1 to enable the s y nchronisation of the reset si g nal; a reset will be g enerated onl y after all bus accesses have been done. this avoids that erroneous data are written into the rams durin g reset. interrupt controller 8 external interrupt channels, 38 internal interrupts, 16 programmable priority levels bit search module searches a word for the position of the first 1 and 0 change bit, starting from the msb. performs the search in 1 cycle. fixed reset vector hardwired reset and mode vector code start at 0f:4000 h voltage regulator generates internal voltage of 3.3 v
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 10 10-apr-01 1.4 features function feature remarks ppg for dimmer (4 channels) 16-bit pwm timer 16 bit down counter, cycle and duty set- ting registers interrupt at triggering, cycle or duty match can be triggered by software or reload timer pwm operation and one-shot operation clock disable internal prescaler allows f res /1, f res /4, f res /16, f res /64 as counter clock required frequencies are 90-300 hz adc (8 channels) successive approximation, internal sam- ple and hold circuit 10-bit resolution, 5 v operation, (conversion time: 178 cycles of clkp) program selectable analogue input chan- nels: single conversion mode continuous conversion mode stop conversion mode interrupt at the end of a conversion can be used to activate dma transfer activation by software prescaling is done internally clock disable basic interval timer (3 channels) 16-bit reload timer, includes clock prescaler (f res /2 1 , f res /2 3 , f res /2 5 ) can (2 channels) conforms to can specification version 2.0 a and b automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and ids supports multiple messages flexible configuration of acceptance filter- ing: full bit compare / full bit mask / two partial bit masks supports up to 1 mb/s clock disable can allows tseg2 = rsjw setting
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 11 10-apr-01 external interrupt (8 channels) can be programmed to be edge sensitive or level sensitive interrupt masking and request pending bits per channel i 2 c-1 for standard mode master or slave transmission arbitration function clock synchronization function slave address and general call address detect function transfer direction detect function start condition repeat generation and detection function bus error detect function compatible to i 2 c standard mode specifi- cation (operation up to 100 khz, 7 bit addressing) includes clock divider functionality clock disable only i 2 c-1 or i 2 c-2 can be used, not both in parallel. bit 0 of f362md will be used to decide which module is connected to the scl and sda pads. by default it is i 2 c-1. i 2 c-2 for standard and fast mode master or slave transmission arbitration function clock synchronization function slave address and general call address detect function transfer direction detect function start condition repeat generation and detection function bus error detect function compatible to i 2 c standard and fast mode specification (operation up to 400 khz, 10 bit addressing) includes clock divider functionality clock disable only i 2 c-1 or i 2 c-2 can be used, not both in parallel. bit 0 of f362md will be used to decide which module is connected to the scl and sda pads. by default it is i 2 c-1. scl and sda lines include optional noise filter. the noise filter allows the suppression of spikes in the range of 1 to 1.5 cycles of clkp. communication on the i2c bus between other connected devices is not possible if mb91f36xga is not connected to the power supply. 16-bit input capture (icu) (4 channels) rising edge, falling edge or rising & falling edge sensitive two 16-bit capture registers signals an interrupt at external event clock disable 16-bit output compare ocu (2 channels) signals an interrupt when a match with of 16-bit io timer occurs an output signal can be generated clock disable
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 12 10-apr-01 free running timer (2 channels for icu and ocu modules) 16-bit free running timer, signals an inter- rupt when overflow or match with compare register_0 includes prescaler (f res /2 2 , f res /2 4 , f res / 2 5 , f res /2 6 ) timer data register has r/w access clock disable alarm comparator (ov/uv detection) monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds status is readable, interrupts can be masked separately clock disable uses external 4:1 voltage divider power down reset monitors vdd and generates a reset if vdd is less than a defined threshold volt- age disabled in rtc and stop modes serial io sio synchronous serial interface (2 channels) + sio-prescaler (2 channels) serial io transfer can be started from msb or lsb supports internal clock synchronized transfer and external clock synchronized transfer prescaler for shift clock allows: f res /3, f res /4, f res /5, f res /6, f res /7, f res /8 clock disable supports positive and negative clock edge synchronization uart (1 channel) u-timer (1 per uart) serial i/o port for performing asynchro- nous (start-stop synchronization) com- munication full duplex, double buffering supports multi-processor mode variable data length (7/8 bit) 1 or 2 stop bits error detection function (parity, framing, overrun) interrupt function nrz type transfer format baud rate generated by u-timer 16-bit timer to generate the required uart clock: f res /2 5 ,,~f res /2 21 (asynchr. mode) clock disable polarity of the port signals for receive and transmit is programma- ble
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 13 10-apr-01 real time clock (rtc) (watch timer) facility to correct oscillation deviation read/write accessible second/minute/ hour registers can signal interrupts every second/ minute/hour/day internal clock divider and prescaler pro- vide exact 1s clock this clock is based on the 4 mhz oscilla- tor or if the subclock option is selected on the 32 khz subclock clock disable prescaler values are 1e847f h , and 4000 h for 4mhz and 32.768khz respectively. 32khz subclock + calibration unit in rtc mode, the rtc module can be driven by either 4mhz or 32khz oscilla- tor, depending on the configuration. additional hardware which allows calibra- tion of the 32khz clock based on the 4mhz clock is built in. this function is only available on mb91f368ga.
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 14 10-apr-01 1.5 pin assignment MB91F367Ga 120-pin plastic qfp index MB91F367Ga avcc avrh an7 an6 an5 an4 an3 an2 an1 an0 v dd vss pr0 pr1 pr2 pr3 vdd pr4 pr5 pr6 pr7 vss ps0 ps1 ps2 ps3 vdd ps4 ps5 ps6 ps7 vss v dd 1 vss sda scl sot4 sin4 sck4 sin3 sot3 sck3 ocpa0 ocpa1 ocpa2 ocpa3 v d d vss tx0 rx0 tx1 rx1 sin0 sot0 pq2 x0 x1 90 91 61 60 30 31 120 vss avss nc cputestx vss v dd int0 int1 int3 int4 int6 int7 in0 out0 out1 vss md0 md1 md2 initx monclk v dd v d d vss v d d vss pq3 in3 in2 in1 v d d vss pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pg5 pg0 pg1 pg2 uart can pwm sio 4 mhz osc. ocu icu ext. int. adc i 2 c di g ital io-ports di g ital i/o-ports testx boot alarm pi3 pg4 pg3 po4 po5 po6 po7 vss v d d v dd vcc3c pm0 pm1 int2 int5 nc no subclock
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 15 10-apr-01 1.6 pin assignment mb91f368ga 120-pin plastic qfp index mb91f368ga avcc avrh an7 an6 an5 an4 an3 an2 an1 an0 v dd vss pr0 pr1 pr2 pr3 vdd pr4 pr5 pr6 pr7 vss ps0 ps1 ps2 ps3 vdd ps4 ps5 ps6 ps7 vss v dd 1 vss sda scl sot4 sin4 sck4 sin3 sot3 sck3 ocpa0 ocpa1 ocpa2 ocpa3 v d d vss tx0 rx0 tx1 rx1 sin0 sot0 pq2 x0 x1 90 91 61 60 30 31 120 vss avss x0a x1a cputestx vss v dd int0 int1 int2 int3 int4 int5 int6 int7 in0 out0 out1 vss md0 md1 md2 initx monclk v dd v d d vss v d d vss pq3 in3 in2 in1 v d d vss pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pg5 pg0 pg1 pg2 uart can pwm sio 4 mhz osc. ocu icu ext. int. adc i 2 c digital io-ports digital i/o-ports testx boot alarm pi3 pg4 pg3 po4 po5 po6 po7 vss v d d v dd vcc3c pm0 pm1 32khz osc. subclock
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 16 10-apr-01 1.7 i/o pins and their functions table 1.7a pinning pin no. qfp120 pin name i/o general purpose i/o port circuit type function 1vdd 2vss 3 pj4 i/o pj4 a digital io-port 4 pj5 i/o pj5 a digital io-port 5 pj6 i/o pj6 a digital io-port 6 pj7 i/o pj7 a digital io-port 7 pi3 i/o pi3 a digital io-port 8vdd 9vss 10 pm0 i/o pm0 a digital io-port 11 pm1 i/o pm1 a digital io-port 12 sda i/o pm2 y i2c sda (no internal pull-up!) 13 scl i/o pm3 y i2c scl (no internal pull-up!) 14 vdd 15 vss 16 avrh r analog voltage ref. high 17 avcc analog vcc 18 avss/avrl ana.volt.ref.low/an.vss 19 an0 i/o ph0 b adc input 20 an1 i/o ph1 b adc input 21 an2 i/o ph2 b adc input 22 an3 i/o ph3 b adc input 23 an4 i/o ph4 b adc input 24 an5 i/o ph5 b adc input 25 an6 i/o ph6 b adc input 26 an7 i/o ph7 b adc input 27 x0a i i 32 khz oscillator pin (mb91f368ga) n.c. not connected (MB91F367Ga) 28 x1a o i 32 khz oscillator pin (mb91f368ga) n.c. not connected (MB91F367Ga) 29 alarm i d alarm comparator input 30 vss 31 boot i/o p93 a boot pin 32 testx i e test mode pin 33 cputestx i e test mode pin 34 vdd 35 x0 i h 4 mhz oscillator pin 36 x1 o h 4 mhz oscillator pin 37 vss 38 monclk o g clock output 39 int0 i/o pk0 a ext. interrupt 40 int1 i/o pk1 a ext. interrupt 41 int2 i/o pk2 a ext. interrupt 42 int3 i/o pk3 a ext. interrupt
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 17 10-apr-01 43 int4 i/o pk4 a ext. interrupt 44 int5 i/o pk5 a ext. interrupt 45 int6 i/o pk6 a ext. interrupt 46 int7 i/o pk7 a ext. interrupt 47 vdd a supply pin for internal voltage regulator 48 vcc3/c capacitor pin for v. reg. 49 vss 50 in0 i/o pl0 a icu input 51 in1 i/o pl1 a icu input 52 in2 i/o pl2 a icu input 53 in3 i/o pl3 a icu input 54 out0 i/o pl4 a ocu output 55 out1 i/o pl5 a ocu output 56 vdd supply pin for internal voltage regulator 57 md0 i t mode pin 58 md1 i t mode pin 59 md2 i t mode pin 60 initx i u initial 61 vdd supply pin for internal voltage regulator 62 vss 63 sot4 i/o pn0 a sio output 64 sin4 i/o pn1 a sio input 65 sck4 i/o pn2 a sio clock 66 sin3 i/o pn3 a sio input 67 sot3 i/o pn4 a sio output 68 sck3 i/o pn5 a sio clock 69 vss 70 ocpa0 i/o po0 a ppg output 71 ocpa1 i/o po1 a ppg output 72 ocpa2 i/o po2 a ppg output 73 ocpa3 i/o po3 a ppg output 74 po4 i/o po4 a digital io-port 75 po5 i/o po5 a digital io-port 76 po6 i/o po6 a digital io-port 77 po7 i/o po7 a digital io-port 78 tx0 i/o pp0 q can tx output 79 rx0 i/o pp1 q can rx output 80 tx1 i/o pp2 q can tx output 81 rx1 i/o pp3 q can rx output 82 vdd 83 vss 84 sin0 i/o pq0 a uart input 85 sot0 i/o pq1 a uart output 86 pq2 i/o pq2 a digital io-port 87 pq3 i/o pq3 a digital io-port 88 pg0 i/o pg0 a digital io-port 89 pg1 i/o pg1 a digital io-port table 1.7a pinning pin no. qfp120 pin name i/o general purpose i/o port circuit type function
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 18 10-apr-01 remark: pin 31 ( boot ) should be low b y default ( pull down resistor ) . to avoid disturbances in case of reset/boot it should preferabl y onl y be used as output b y an y application. 90 pg2 i/o pg2 a digital io-port 91 pg3 i/o pg3 a digital io-port 92 pg4 i/o pg4 a digital io-port 93 pg5 i/o pg5 a digital io-port 94 vdd 95 vss 96 pr0 i/o pr0 k1 digital io-port 97 pr1 i/o pr1 k1 digital io-port 98 pr2 i/o pr2 k1 digital io-port 99 pr3 i/o pr3 m1 digital io-port 100 hvdd vdd for ports r and s 101 pr4 i/o pr4 k1 digital io-port 102 pr5 i/o pr5 k1 digital io-port 103 pr6 i/o pr6 k1 digital io-port 104 pr7 i/o pr7 m1 digital io-port 105 vss 106 ps0 i/o ps0 k1 digital io-port 107 ps1 i/o ps1 k1 digital io-port 108 ps2 i/o ps2 k1 digital io-port 109 ps3 i/o ps3 m1 digital io-port 110 hvdd vdd for ports r and s 111 ps4 i/o ps4 k1 digital io-port 112 ps5 i/o ps5 k1 digital io-port 113 ps6 i/o ps6 k1 digital io-port 114 ps7 i/o ps7 m1 digital io-port 115 vss 116 vdd 117 pj0 i/o pj0 a digital io-port 118 pj1 i/o pj1 a digital io-port 119 pj2 i/o pj2 a digital io-port 120 pj3 i/o pj3 a digital io-port table 1.7a pinning pin no. qfp120 pin name i/o general purpose i/o port circuit type function
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 19 10-apr-01 table 1.7b circuit types circuit type description a i/o, ioh=4 ma / iol=4 ma, cmos automotive schmitt-trigger input, stop control b i/o, ioh=4 ma / iol=4 ma, cmos automotive schmitt-trigger input, analog input, stop control d analog input e cmos schmitt-trigger input, 50k pull-up g tristate output, ioh=4 ma / iol=4 ma h 4 mhz oscillator pin i 32khz oscillator pin k1 i/o, ioh=30 ma / iol=30 ma, cmos automotive schmitt-trigger input, stop control m1 i/o, ioh=30 ma / iol=30 ma, cmos automotive schmitt-trigger input, analog input, stop con- trol q i/o, ioh=4 ma / iol=4 ma, cmos input, stop control r avrh input t cmos input, can withstand v id for flash programming u cmos schmitt-trigger input, 50k pull-up y i/o, ioh=3ma / iol=3ma (i2c), cmos input, stop control
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 20 10-apr-01 1.8 flash memory mode of MB91F367Ga/f368ga to enter the flash memor y mode set mode pins md0 to md2 to 111. assert initx for at least 500 ns to enter this mode. the followin g tables show the pins which are re q uired for the pro g rammin g procedure and also describe the states for the pins not used in flash memor y mode. most of the not used pins are in their reset state ( hi g h-z outputs, enabled inputs ) . to prevent misbehavior or dama g e these pins must be tied to vdd or vss throu g h resistors - see followin g tables for details. aside from the functional pins described below all power pins should be connected to a power suppl y in the specified ran g e, capacitances should be connected to the vcc3c pin as recom- mended. table 1: flash control signals MB91F367Ga/f368ga mbm29lv400c notes pin number normal function flash memory mode 31 boot we we 32 testx byte byte 33 cputestx tmodx pull up 38 monclk ry/by ry/by 39-46 int0-int7 d24 to d31 dq8 to dq15 50 in0 ce ce 51 in1 oe oe 52 in2 d20 dq4 53 in3 d21 dq5 54 out0 d22 dq6 55 out1 d23 dq7 57 md0 vda9 a9 (v id ) 58 md1 vdrs reset (v id ) 59 md2 vdoe oe (v id ) 60 initx reset reset 91-93 pg3-pg5 a16-a18 a15-a17 96 pr0 a0 a-1 97 pr1 a1 a0 98 pr2 a2 a1 99 pr3 a3 a2
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 21 10-apr-01 101 pr4 a4 a3 102 pr5 a5 a4 103 pr6 a6 a5 104 pr7 a7 a6 106 ps0 a8 a7 107 ps1 a9 a8 108 ps2 a10 a9 109 ps3 a11 a10 111 ps4 a12 a11 112 ps5 a13 a12 113 ps6 a14 a13 114 ps7 a15 a14 117 to 120 pj0-pj3 d16 to d19 dq0 to dq3 table 2: pins not used in flash memory mode MB91F367Ga/f368ga pin number normal function pin state notes 35 x0 input pull up 36 x1 output leave open 66 sin3 output leave open 67 sot3 output leave open 68 sck3 output leave open 27 x0a input pull up 28 x1a output leave open 29 alarm input pull up all other signals input pull up table 1: flash control signals MB91F367Ga/f368ga mbm29lv400c notes pin number normal function flash memory mode
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 22 10-apr-01 chapter 2 additional information 2.1 flash interface 2.1.2 flash control status register (fmcs) bit 7: faccen: controls read access mode to flash 0: s y nchronous read access usin g atdin and eqin si g nals - recommended settin g 1: as y nchronous read access bits 6,5: reserved when writin g to these bits alwa y s write "11" bit 4: rdyeg: when the auto al g orithm of flash memor y is finished, this bit is set to '1'. this bit is cleared b y readin g it. 0: auto al g orithm not y et finished 1: auto al g orithm finished bit 3: rdy: the state of auto al g orithm 0:the state of the auto al g orithm is write/read. can't accept write/read/delete. 1:it is possible to accept write/read/delete. bit 2: rdyi: reserved bit bit 1: we: this bit is used to control writin g and readin g to flash memor y in cpu mode 0: writin g to flash memor y is disabled, read access is 32 bit wide 1: writin g enabled, read access 16 bit wide, auto al g orithm can be used this bit can onl y be written to if rdy is 1. bit 0: lpm: 0: normal mode 1: low power mode, can be used when cpu fre q uenc y is below 5 mhz address bit 7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00007000 h faccen ---- ---- rdyeg rdy rdyi we lpm access r/w r/w r/w r r r/w r/w r/w initial value 1 110x000 value after boot rom 0 110x000
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 23 10-apr-01 2.1.3 flash wait control register (fmwt) bit 6: this bit is reserved, alwa y s set this bit to "0" when writin g to this re g ister. bits 5,4: these bits control the len g th of the hi g h pulse for the atdin si g nal bit 3: eqinh: this bit controls the fallin g ed g e of the eqin si g nal. 0: fallin g ed g e of eqin at fallin g ed g e of fwaitr; 1: fallin g ed g e of eqin half c y cle after fallin g ed g e of fwaitr; bit 2,1,0: wtc2,1,0: wait c y cle bits wtc2-0 are used to insert auto wait c y cles for flash memor y access. addressbit 7 bit6 bit 5bit 4bit 3bit 2bit 1bit 0 0000700 4 h ---- ---- fac1 fac0 eqinh wtc2 wtc1 wtc0 access r/w r/w r/w r/w r/w r/w r/w initial value 0000011 value after boot rom 0010011 fac1 fac0 length of high pulse for atdin 0 0 0.5 cycles of clkb 0 1 1 cycle of clkb 1 0 1.5 cycles of clkb 1 1 2 cycles of clkb wtc2 wtc1 wtc0 wait cycles 000 0 001 1 010 2 011 3 100 4
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 24 10-apr-01 recommended settin g s for fac1, fac0 and wtc2 to wtc0 for read access to the flash memor y : ? without appl y in g clock modulation: ? when appl y in g clock modulation: 101 5 110 6 111 7 clkb unmodulated core clock frequency [mhz] fac1 fac0 eqinh wtc2 wtc1 wtc0 atdin high cycles/wait cycles fmwt 32 001001 0.5 / 109 h 24 000001 0.5 / 101 h 16 000001 0.5 / 101 h clkb core clock frequency [mhz] peak max. frequency fac1 fac0 eqinh wtc2 wtc1 wtc0 atdin high cycles/wait cycles fmwt 32 64 0 1 0 0 1 1 1 / 3 13 h 32 48 0 0 0 0 1 0 0.5 / 2 02 h 24 40 0 0 0 0 1 0 0.5 / 2 02 h 24 32 0 0 1 0 0 1 0.5 / 1 09 h 16 24 0 0 0 0 0 1 0.5 / 1 01 h wtc2 wtc1 wtc0 wait cycles
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 25 10-apr-01 example for flash memor y read access with 1 c y cle for the hi g h time of atdin and 3 wait c y cles : the minimum value for twatd is 10 ns, the minimum value for tweq is 20 ns. the minimum value for trc is 40 ns. the maximum value for tacc is twatd+tweq+5 ns. clkb fa fwaitr atdin fd a1 a2 a3 d1 3 wait cycles 1 cycle atdin high core clock f-bus address f-bus wait atdin for flash f-bus data eqin twatd tweq tacc trc eqin for flash
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 26 10-apr-01 recommended settin g s for wtc2 to wtc0 for write access to the flash memor y , faccen of fmcs should be set to 1 for writin g , so fac1, fac0, eqinh re g ister settin g s then have no meanin g for the write operation : ? without appl y in g clock modulation: ? when appl y in g clock modulatio n: clkb unmodulated core clock frequency [mhz] wtc2 wtc1 wtc0 wait cycles fmwt 32 0 1 0 2 x2 h 24 0 1 0 2 x2 h 16 0 0 1 1 x1 h clkb core clock frequency [mhz] peak max. frequency wtc2 wtc1 wtc0 wait cycles fmwt 32 64 setting not allowed for writing 32 48 1 0 0 4 x4 h 24 40 1 0 0 4 x4 h 24 32 0 1 0 2 x2 h 16 24 0 1 0 2 x2 h
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 27 10-apr-01 2.2 f362 mode register (f362md) bit 15-9: reserved, when writin g to bits 15-9, alwa y s write 0000000 bit 8: iicsel 0: selection of 100 khz i2c interface ( i2c-1 ) 1: selection of 400 khz i2c interface ( i2c-2 ) address bit 15 bit14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00001fe h ---- --- ---- ---- ---- ---- ---- iicsel access r/w r/w r/w r/w r/w r/w r/w initial value 00 0 0 0 0 0
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 28 10-apr-01 2.3 oscillation stabilization time for a mode settin g of md [ 2:0 ] = "000" the followin g settin g s of os1 and os0 bits in the standb y control re g ister ( stcr ) will be implemented: 2.4 subclock rtc32 (clkr2) this re g ister is used to control the rtc32 mode bit for use in subclock s y stem. bit [ 15:11 ] : reserved bit [ 10:9 ] : reserved, alwa y s write 0 back when writin g to these bits. bit 8: rtc32 0: rtc32khi mode, hi g h power mode of internal volta g e re g ulator used in rtc mode 1: rtc32klo mode, low power mode of internal volta g e re g ulator used in rtc mode alwa y s set this bit to 1 when usin g the rtc mode based on the 32 khz subclock. this is onl y available for mb91f368ga. os1 os0 oscillation stabilization wait time time based on 4 mhz oscillator ( f ) 00 f * 2 16 32 ms (initial value) 01 f * 2 11 1 ms 10 f * 2 16 32 ms 11 f * 2 1 1 m s address bit 15 bit14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 000046 h ---- ---- ---- ---- ---- ---- ---- rtc32 access r/w r/w r/w initial value 000
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 29 10-apr-01 2.5 boot rom the followin g settin g s have been implemented in the boot rom of MB91F367Ga/f368ga: ? flash area: 08:0000 to 0f:fff7 ? securit y vector at 0f:fef4 ? securit y vector valid in ran g es 08:0000-0f:ffff ?pro g ram entr y at 0f:4000 ? rom stamp at 05:0500 ?flash re g isters initialized to fmcs=0x60, fmwt=0x13
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 30 10-apr-01 chapter 3 io-map see appendix a. the addresses shown in this table for can re g isters are based on the settin g s for cs7 done in the boot rom. chapter 4 interrupt vector table see appendix b . chapter 5 power-on-sequence all vdd pins should be connected to the same potential. the analo g ue suppl y volta g e ( avcc ) must not be turned on before the di g ital suppl y volta g e. immediatel y after power on alwa y s execute init at the initx pin ( input a low level to the initx pin ) . hold this low level at the initx pin lon g enou g h so that after release of the low level at initx and the passin g of the built in waitin g time stable oscillation of the oscillation circuit is achieved. initx must be pulled low for at least 8 c y cles of the 4 mhz oscillation clock. chapter 6 handling of unused input pins leavin g unused input pins open ma y result in misbehavior or latch up and possible permanent dama g e of the de- vice. therefore the y must be tied to vdd or vss throu g h resistors. in this case those resistors should be more than 2 kohm. unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. the resistor of more than 2 kohm is used to limit currents throu g h the protection diodes. in case of volta g es at the unused pin of 0.3 v or more below vss or 0.3 v or more above vdd currents which could cause latch-up will flow throu g h those diodes. it is possible to use one resistor to connect several pins to vdd or vss. care should be taken not to connect pins from different suppl y volta g e domains to one resistor.
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 31 10-apr-01 chapter 7 emulation device mb91fv360ga can be used as an emulation device for MB91F367Ga/f368ga. MB91F367Ga/f368ga use the followin g resources of mb91fv360ga ( see mb91fv360ga io-map ) : ? reload timer 0 - reload timer 2 ? uart 0 / u-timer 0 ? sio 0 - sio 1 and their prescalers ? i 2 c ( 100khz and 400khz ) ? a/d converter ( channels 0 - 7 ) ? input capture 0 - input capture 3 ? output compare 0 - output compare 1 ? free runnin g counter 0 - free runnin g counter 1 ? real time clock ? 32 khz subclock and calibration unit - mb91f368ga onl y ? pro g rammable pulse generators: pwm control 0, pwm channels 0 - 3 ? power down reset ? alarm comparator ? can0 - can 1 ? user ram 16kb: address ran g e: 03c000-03ffff ? f-bus ram 16kb: address ran g e: 040000-043fff ? i-ram 4kb: address ran g e: 011000-011fff note: because reload timers 3 to 5 are not available on this device, the adc cannot be tri gg ered b y a reload timer - on mb91fv360ga and other devices reload timer 4 is connected to the adc
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 32 10-apr-01 chapter 8 package a qfp-120 packa g e called fpt-120p-m21 ( 0.5 mm pin pitch ) will be used for MB91F367Ga/f368ga. the thermal resistance of this packa g e is 30 de g r. c/w. the maximum allowed ambient temperature is 85 de g r. c, the maximum allowed j unction temperature is 125 de g r.c. under these conditions a maximum power consumption of ( 125 de g r. c - 85 de g r. c ) / 30 c/w = 1.33 w is allowed. the user must make sure that the maximum ambient temperature is not exceeded. for other details about the packa g e see fu j itsu semiconductor packa g e data book. thermal resistance [degr. c/w] theta-ja (junction to ambient) theta-jc (junction to case) 0 m/s 1 m/s 3 m/s 30 27 25 5
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 33 10-apr-01 chapter 9 electrical specification 9.1 absolute maximum ratings * making full use of the allowed static dc current into digital i/os will lead to lower values here. 9.2 operating conditions parameter symbol min. max. unit condition digital supply voltage vdd-vss -0.3 6.0 v storage temperature j st -55 125 c power consumption p tot 1330 mw j ambient = 25 c digital input voltage v idig -0.3 * 5.8 v vss=0v, vdd=5v analog input voltage v ia -0.3 5.8 v vssa=0v, vdda=5v analog supply voltage vdda-vssa -0.3 5.8 v vssa=0v analog reference voltage v refh/l - vssa -0.3 5.8 v vssa=0v static dc current into digital i/o i i/odc -2 2 ma s i i/odc < i soperation parameter symbol min. typ. max. unit condition operating temperature j op -40 85 c supply voltage - digital supply - analog supply vdd-vss vdda-vssa 4.25 1) 4.9 5 5 5.25 5.1 v v internal voltage reg. vdd core =3.3v vssa=0v current consumption -run mode 3) -rtc mode -stop mode i srun i srtc4 isrtc32 i sstop see 0.5 tbd 10 below 1.25 0.5 200 ma ma m a m a f clk =4mhz@ j op =25 c fclk=32khz@ j op=25 c f clk =0 @ j op =25 c ram data retention voltage vdd-vss 3.0 v
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 34 10-apr-01 alarm comparator -threshold voltages - overvoltage - undervoltage - switching hysteresis - alarm sense time - input resistance v ta h v ta l v tahys t as r in 4 / 5 vdda -5% 2 / 5 vdda -5% 12.5 5 4 / 5 vdda 2 / 5 vdda 25 4 / 5 vdda +5% 2 / 5 vdda +5% 50 10 v v mv m s m w (external 4:1 divider) at v ta h , v ta l power down reset -threshold voltage - switching hysteresis - reset sense time v tpor v tporhys t rs 3.5 20 4.0 50 4.5 80 10 v mv m s digital inputs 2) cmos (type:q) - high voltage range - low voltage range cmos schmitt-trigger (types: e, u) - high voltage range - low voltage range cmos automotive schmitt-trigger (types: a, b, w, x) - high voltage range - low voltage range - hysteresis voltage - input capacitance - input leakage current - pull up resistor v ih v il v ih v il v ih v il c in i il r up1 0.65*vdd vss 0.8*vdd vss 0.8*vdd vss -1 0.5 50 vdd 0.25*vdd vdd 0.2*vdd vdd 0.5*vdd 0.6*vdd 16 1 v v v v v v v v pf m a k w vmin=4.25v vmin=4.75v ty p e s : e , u j op=25 c digital outputs - output "h" voltage - output "l" voltage v oh v ol vdd-0.5 vss vdd vss+0.4 v v i load = 4ma i load = - 4ma
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 35 10-apr-01 1) this is only valid if the integrated power-down reset circuit is switched-off, else a reset can be triggered at volt- ages less or equal than 4.5 v (see spec items for power-down reset) 2) valid for bidirectional tristate i/o pad cell 3) ii srun describes the current consumption of the mcu core only and has been determined by setting the clock frequencies shown below and running an endless loop from internal flash memory which generates activity on all internal buses. a procedure to calculate the overall power consumption is also shown below. 4) the protection diodes at the analog inputs are connected to the digital supply voltage adc inputs 4 ) - reference voltage input - input voltage range - input resistance - input capacitance - impedance of exter- nal output driving the adc input - input leakage current v refh v refl v imax v imin r i c i i il v refl +3 vssa v refl -1 vdda v refh -3 v refh 3.6 30 4.0 1 v v v v k w pf k w m a @ sampling time of 1.6 m s j op=25 c ppg - output voltage - output current v outhigh v outlow i out vdd-0.5 vss 4 vdd vss+0.4 v v ma i 2 c bus interface - output voltage - output current - input threshold voltage v outhigh v outlow i out v ih v il vss 3 0.65*vdd vss vdd vss+0.4 vdd 0.25*vdd v v ma v v open drain output i outlow = 3ma lock-up time pll1 (4mhz->1664mhz) 1ms esd protection (human body model mil883-b compliant) v surge 2kv r discharge =1.5k w c discharge = 100pf r i c i
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 36 10-apr-01 9.3 run mode current/power consumption the power dissipation durin g normal operation is determined b y the total power dissipation of the internal lo g ic p c , the dissipation from analo g modules p a and the power dissipation p io of the i/o buffers. amon g the i/o buff- ers the dissipation caused b y the stepper motor drivers p smc should be taken into special consideration. so the overall power consumption p d will be calculated as a sum of pc + p a + p io . 9.3.1 logic power consumption the followin g formula can be used to calculate the maximum core current consumption when the pll is used dependin g on the fre q uenc y settin g s for the internal clocks: icc = 3.45 [ ma/mhz ] * clkb [ mhz ] + 2.52 [ ma/mhz ] * clkp [ mhz ] + 0.72 [ ma/mhz ] * clkt [ mhz ] + 35.5 ma. if clock modulation is used the followin g value must be added to this result: 0.24 [ ma/mhz ] * clkb [ mhz ] . this results in the followin g values: . note: higher frequency settings cannot be allowed in the package currently used. for higher frequency settings the maximum power consumption would exceed the maximum allowed value of 1.33w. in addition to this power consumption of the mcu core lo g ic the followin g contributions to the overall power con- sumption have to be considered: clock frequencies [mhz] maximum core current consumption [ma] logic power consumption p c at 5.25 v [mw] remarks clkb clkp clkt 32 16 16 205 1.08 24 24 24 202 1.06 24 12 12 163 0.86 16 16 16 146 0.77 2 2 2 40 0.21 no pll, no clock modulation 0.125 0.125 0.125 30 0.16 no pll, no clock modulation
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 37 10-apr-01 9.3.2 analog power consumption to calculate the analo g power consumption p a , the current contributions of the active modules have to be multi- plied b y the maximum analo g suppl y volta g e of 5.1 v. 9.3.3 i/o power consumption i/o buffers : the power dissipation ( p io ) ( at 5.25 v ) of the i/o buffers is represented as the sum of the d y namic power dissipa- tion ( p ac ) and the static power consumption ( p dc ) . p io = p ac * 1.1 + p dc the followin g table lists values for p ac : p ac = p ib * in * f * operatin g rate + p ob * on * f * operatin g rate p ib : power consumption of input buffers and bidirectional inputs p ob : power consumption of output buffers and bidirectional outputs in: total number of input buffers and bidirectional buffer inputs on: total number of output buffers and bidirectional buffer outputs f: s y stem fre q uenc y operatin g rate: 1.0 if all buffers are switched simultaneousl y at s y stem fre q uenc y p dc is the caused b y off chip loads which are drawin g static currents. p dc = vo * io * dc n module maximum current consumption remarks dac 1 ma / channel adc 7 ma power down reset 0.5 ma alarm comparator 0.5 ma buffer t y pe power consumption unit normal input 12.4 m w/mhz @ 5.0v bidirectional input 4 ma bidirectional output 194 + 25 c l 4 ma output 8 ma bidirectional output 353 + 25 c l 8 ma output
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 38 10-apr-01 vo: output volta g e drop - usuall y 0.4 v io: output current - usuall y 4 ma dc n : number of output buffers and bidirectional buffers drivin g off chip loads causin g static currents.
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 39 10-apr-01 9.4 converter characteristics ? a/d converter 9.5 clock settin g s note: because of the maximum allowed current consum p tion settin g all clocks to their maximum values is not p ossible in the current p acka g e. see calculation of p ower consum p tion above. however, clock modulation u p to the fre q uencies s p ecified above is still p ossible. in the case of modulation over 58 mhz no odd division factor ( 3,5,7,9,11,13 ) for clkt must be selected. parameter symbol rating unit remark minimum typical maximum resolution 10 bit conversion error +/- 5.0 lsb overall error non-linearity +/-2.5 lsb differential non-linearity +/-1.9 lsb zero reading voltage v 0t avrl -3.5 avrl+0.5 avrl+4.5 lsb full scale reading voltage v fst avrh-5.5 avrh-1.5 avrh+2.5 lsb input current (vdda) ia 3.0 7.0 ma reference voltage current ir 1.6 2.6 ma clock domain clock name max. frequency remark core clkb 64 mhz for supply voltage between 4.25 and 5.25 v 32 mhz for supply voltage between 4.25 and 3.5 v resource bus clkp 32 mhz ext. bus clkt 32 mhz clock for can canclk 32 mhz
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 40 10-apr-01 9.6 clock modulator settings the clock modulator is a module to reduce eme (electromagnetic emission) problems by spreading the energy of the system over a wide range of the frequency spectrum. in order to allow optimization of system performance versus eme reduction, the modulator is programmable over a wide modulation range. detailed information about clock modulator operation and settings is available from fujitsu on request. clock modulator in p ut fre q uenc y [mhz] number of o p erational settin g s for clock modulator on 32 8 on 24 11 on 16 14
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 41 10-apr-01 appendix a i/o map version 1.3, 2000/02/28 table a lists the addresses for the registers used by the internal peripheral functions of the MB91F367Ga/f368ga. ? how to read the i/o map read/write attribute register initial value after a reset (bit initial values) 1: initial value 1, 0: initial value 0, x: initial value x (indeterminate), indicates non-existent bits register name (the register in column 1 is at location 4n, the register in column 2 at 4n+1, and so on.) location of far left of register (+0). +1, +2, and +3 each increment the location by one. when performing word access, the register in column 1 is placed at the msb end of the data. precautions: ? do not use rmw instructions on registers containing write-only (w) bits. rmw instructions(rmw:read-modify-write) and rj, @ri or rj, @ri eor rj, @ri andh rj, @ri orh rj, @ri eorh rj, @ri andb rj, @ri orb rj, @ri eorb rj, @ri bandl #u4, @ri borl #u4, @ri beorl #u4, @ri bandh #u4, @ri borh #u4, @ri beorh #u4, @ri ? the data in reserved areas and areas marked ? is indeterminate. do not use those areas! address register block +0 +1 +2 +3 000000 h reserved t-unit por t data register 000004 h reserved 000008 h reserved 00000c h reserved address register internal peripheral +0 +1 +2 +3 000014 h pdrg [r/w] pdrh [r/w] pdri [r/w] port data register xxxxxxxx xxxxxxxx ---- xxxx
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 42 10-apr-01 000010 h pdrg [r/w] xxxxxxxx pdrh [r/w] xxxxxxxx pdri [r/w] x - - - x - - - pdrj [r/w] xxxxxxxx r-bus port data register 000014 h pdrk [r/w] xxxxxxxx pdrl [r/w] xxxxxxxx pdrm [r/w] - - - - xxxx pdrn [r/w] - - xxxxxx 000018 h pdro [r/w] xxxxxxxx pdrp [r/w] - - xxxxx pdrq [r/w] - - xxxxx pdrr [r/w] xxxxxxxx 00001c h pdrs [r/w] xxxxxxxx 000020 h | 00003c h reserved 000040 h eirr [r/w] 00000000 enir [r/w] 00000000 elvr [r/w] 00000000 00000000 ext int/nmi 000044 h dicr [r/w] - - - - - - - 0 hrcl [r/w] 0 - - 11111 clkr2 [r/w] - - - - - - 000 reserved dlyi/i-unit rtc 000048 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 00004c h ________ tmcsr0 [r/w] - - - - 0000 - - - 00000 000050 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 000054 h ________ tmcsr1 [r/w] - - - - 0000 - - - 00000 000058 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 00005c h ________ tmcsr2 [r/w] - - - - 0000 - - - 00000 000060 h ssr0 [r/w] 00001 - 00 sidr0 [r/w] xxxxxxxx scr0 [r/w] 00000100 smr0 [r/w] 00 - - 0 - 0 - uart0 000064 h uls0 [r/w] - - - - 0000 000068 h utim0/utimr0 [r/w] 00000000 00000000 drcl0 [w] - - - - - - - - utimc0 [r/w] 0 - - - 0 - 01 u-timer 0 00006c h ________ reserved 000070 h 000074 h 000078 h 00007c h 000080 h address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 43 10-apr-01 000084 h smcs0 [r/w] 00000010 - - - - 00-0 sio 0 ses0 [r/w] - - - - - - 00 sdr0 [r/w] 00000000 000088 h smcs1 [r/w] 00000010 - - - - 00 - 0 sdr1 [r/w] 00000000 sio 1 ses1 [r/w] - - - - - - 00 00008c h cdcr0 [r/w] 0 - - - 1111 reserved cdcr1 [r/w] 0 - - - 1111 reserved sio 0/1 prescaler 000090 h reserved 000094 h ibcr [r/w] 00000000 ibsr [r] 00000000 iadr [r/w] -xxxxxxx iccr [r/w] - - 0xxxxx i2c (old) -> new i2c from address 0x184 000098 h idar [r/w] xxxxxxxx idbl [r/w] -------0 00009c h admd [r/w,w] - - - x0000 adch [r/w] 00000000 adcs [r/w,w] 0000 - - 00 a/d converter 0000a0 h adcd [r/w] 000000xx xxxxxxxx adbl [r/w] - - - - - - - 0 0000a4 h ________ reserved 0000a8 h ________ 0000ac h iotdbl0 [r/w] - - - - - 000 ics01 [r/w] 00000000 iotdbl1 [r/w] - - - - - 000 ics23 [r/w] 00000000 input capture 0,1,2,3 0000b0 h ipcp0 [r] xxxxxxxx xxxxxxxx ipcp1 [r] xxxxxxxx xxxxxxxx 0000b4 h ipcp2 [r] xxxxxxxx xxxxxxxx ipcp3 [r] xxxxxxxx xxxxxxxx 0000b8 h ocs01 [r/w] - - - 0 - - 00 0000 - - 00 reserved output com- pare 0,1 0000bc h occp0 [r/w] xxxxxxxx xxxxxxxx occp1 [r/w] xxxxxxxx xxxxxxxx 0000c0 h ________ reserved 0000c4 h 0000c8 h tcdt0 [r/w] xxxxxxxx xxxxxxxx ________ tccs0 [r/w] - 0000000 free running counter 0 for icu/ocu 0000cc h tcdt1 [r/w] xxxxxxxx xxxxxxxx ________ tccs1 [r/w] - 0000000 free running counter 1 for icu/ocu 0000d0 h address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 44 10-apr-01 0000d4 h ________ reserved 0000d8 h 0000dc h 0000e0 h 0000e4 h 0000e8 h 0000ec h 0000f0 h 0000f4 h wtdbl [r/w] - - - - - - - 0 wtcr [r/w] 00000000 000 - 0000 real time clock (watchtimer) 0000f8 h wtbr [r/w] - - xxxxxx xxxxxxxx xxxxxxxx 0000fc h wthr [r/w] - - - 00000 wtmr [r/w] - - 000000 wtsr [r/w] - - 000000 000100 h ________ reserved 000104 h 000108 h 00010c h 000110 h 000114 h 000118 h gcn10 [r/w] 00110010 00010000 pdbl0 [r/w] - - - 00000 gcn20 [r/w] - - - - 0000 pwm control 0 00011c h ________ reserved 000120 h ptmr0 [r] 11111111 11111111 pcsr0 [w] xxxxxxxx xxxxxxxx pwm0 000124 h pdut0 [w] xxxxxxxx xxxxxxxx pcnh0 [r/w] 0000000 - pcnl0 [r/w] 000000 - 0 000128 h ptmr1 [r] 11111111 11111111 pcsr1 [w] xxxxxxxx xxxxxxxx pwm1 00012c h pdut1 [w] xxxxxxxx xxxxxxxx pcnh1 [r/w] 0000000 - pcnl1 [r/w] 000000 - 0 000130 h ptmr2 [r] 11111111 11111111 pcsr2 [w] xxxxxxxx xxxxxxxx pwm2 000134 h pdut2 [w] xxxxxxxx xxxxxxxx pcnh2 [r/w] 0000000 - pcnl2 [r/w] 000000 - 0 address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 45 10-apr-01 000138 h ptmr3 [r] 11111111 11111111 pcsr3 [w] xxxxxxxx xxxxxxxx pwm3 00013c h pdut3 [w] xxxxxxxx xxxxxxxx pcnh3 [r/w] 0000000 - pcnl3 [r/w] 000000 - 0 000140 h ________ reserved 000144 h 000148 h 00014c h 000150 h 000154 h 000158 h 00015c h 000160 h 000164 h cmcr [r/w] 11111111 0000000 cmpr [r/w] ----1001 1---0001 clock modula- tion 000168 h cmls0 [r/w] 01110111 1111111 cmls1 [r/w] 01110111 1111111 00016c h cmls2 [r/w] 01110111 1111111 cmls3 [r/w] 01110111 1111111 000170 h cmlt0 [r/w] -----100 00000010 cmlt1 [r/w] 11110100 00000010 000174 h cmlt2 [r/w] -----100 00000010 cmlt3 [r/w] -----100 00000010 000178 h cmac [r/w] 11111111 1111111 cmts [r/w] --000001 01111111 00017c h pdrcr [r/w] - - - - - 000 power down reset 000180 h accdbl[r/w] - - - - - - - 0 acsr [r/w] - - - xxx00 alarm compa- rator 000184 h ibcr2 [r/w] 00000000 ibsr 2 [r] 00000000 itbah [r/w] - - - - - - 00 itbal [r/w] 00000000 i2c (new) (*) old and new i2c share this bit! 000188 h itmkh [r/w] 00 - - - - 11 itmkl [r/w] 11111111 ismk [r/w] 01111111 isba [r/w] - 0000000 00018c h idarh [-] 00000000 idar 2 [r/w] 00000000 iccr 2 [r/w] - 0011111 idbl2(*) [r/w] - - - - - - - 0 000190h cucr [r/w] - - - - - - - - - - - 0 - -00 cutd [r/w] 10000000 00000000 calibration unit of 32khz oscillator (only on f368ga) 000194h cutr1 [r] -------- 00000000 cutr2 [r] 00000000 00000000 address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 46 10-apr-01 000198 h | 0001f8 h -----1 reserved 0001fc h f362md [r/w] 00000000 f362 mode reg 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h | 00023c h ________ 000240 h dmacr [r/w] 00--0000 -------- -------- -------- 000244 h | 0003ec h ________ reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 47 10-apr-01 000400 h ddrg [r/w] 00000000 ddrh [r/w] 00000000 ddri [r/w] ----0--- ddrj [r/w] 00000000 r-bus port direction register 000404 h ddrk [r/w] 00000000 ddrl [r/w] 00000000 ddrm [r/w] ----0000 ddrn [r/w] --000000 000408 h ddro [r/w] 00000000 ddrp [r/w] ----0000 ddrq [r/w] --000000 ddrr [r/w] 00000000 00040c h ddrs [r/w] 00000000 000410 h pfrg [r/w] 00000000 pfrh [r/w] 00000000 pfri [r/w] ----0--- pfrj [r/w] 00000000 r-bus port function register 000414 h pfrk [r/w] 00000000 pfrl [r/w] 00000000 pfrm [r/w] ----0000 pfrn [r/w] --000000 000418 h pfro [r/w] 00000000 pfrp [r/w] 00000000 pfrq [r/w] --000000 pfrr [r/w] 00000000 00041c h pfrs [r/w] 00000000 000420 h | 00043c h ________ reserved address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 48 10-apr-01 000440 h icr00 [r/w] ---11111 icr01 [r/w] ---11111 icr02 [r/w] ---11111 icr03 [r/w] ---11111 interrupt con- trol unit 000444 h icr04 [r/w] ---11111 icr05 [r/w] ---11111 icr06 [r/w] ---11111 icr07 [r/w] ---11111 000448 h icr08 [r/w] ---11111 icr09 [r/w] ---11111 icr10 [r/w] ---11111 icr11 [r/w] ---11111 00044c h icr12 [r/w] ---11111 icr13 [r/w] ---11111 icr14 [r/w] ---11111 icr15 [r/w] ---11111 000450 h icr16 [r/w] ---11111 icr17 [r/w] ---11111 icr18 [r/w] ---11111 icr19 [r/w] ---11111 000454 h icr20 [r/w] ---11111 icr21 [r/w] ---11111 icr22 [r/w] ---11111 icr23 [r/w] ---11111 000458 h icr24 [r/w] ---11111 icr25 [r/w] ---11111 icr26 [r/w] ---11111 icr27 [r/w] ---11111 00045c h icr28 [r/w] ---11111 icr29 [r/w] ---11111 icr30 [r/w] ---11111 icr31 [r/w] ---11111 000460 h icr32 [r/w] ---11111 icr33 [r/w] ---11111 icr34 [r/w] ---11111 icr35 [r/w] ---11111 000464 h icr36 [r/w] ---11111 icr37 [r/w] ---11111 icr38 [r/w] ---11111 icr39 [r/w] ---11111 000468 h icr40 [r/w] ---11111 icr41 [r/w] ---11111 icr42 [r/w] ---11111 icr43 [r/w] ---11111 00046c h icr44 [r/w] ---11111 icr45 [r/w] ---11111 icr46 [r/w] ---11111 icr47 [r/w] ---11111 000470 h | 00047c h ________ 000480 h rsrr [r/w] 10000000 stcr [r/w] 00110011 tbcr [r/w] x0000x00 ctbr [w] xxxxxxxx clock control unit 000484 h clkr [r/w] 00000000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h | 0005fc h ________ reserved 000600 h ________ reserved 000604 h 000608 h 00060c h address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 49 10-apr-01 000610 h ________ reserved 000614 h 000618 h 00061c h 000620 h 000624 h 000628 h | 00063f h ________ reserved 000640 h asr0 [w] 00000000 00000000 amr0 [w] 11111000 11111111 t-unit 000644 h asr1 [w] 00000000 00000000 amr1 [w] 00000000 00000000 000648 h asr2 [w] 00000000 00000000 amr2 [w] 00000000 00000000 00064c h asr3 [w] 00000000 00000000 amr3 [w] 00000000 00000000 000650 h asr4 [w] 00000000 00000000 amr4 [w] 00000000 00000000 000654 h asr5 [w] 00000000 00000000 amr5 [w] 00000000 00000000 000658 h asr6 [w] 00000000 00000000 amr6 [w] 00000000 00000000 00065c h asr7 [w] 00000000 00000000 amr7 [w] 00000000 00000000 000660 h amd0 [r/w] -00xx111 amd1 [r/w] -xxxxxxx amd2 [r/w] --xxxxxx amd3 [r/w] --xxxxxx 000664 h amd4 [r/w] --xxxxxx amd5 [r/w] --xxxxxx amd6 [r/w] -xxxxxxx amd7 [r/w] -xxxxxxx 000668 h cse 11000011 ________ ________ ________ 00066c h ________ ________ 000670 h che 11111111 ________ ________ 000674 h | 0007f8 h ________ reserved 0007fc h ________ modr [w] xxxxxxxx ________ ________ mode regis- ter address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 50 10-apr-01 000800 h | 000b6c h ________ reserved 001000 h dmasa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h | 003ffc h ________ reserved 004000 h | 006fff h ________ reserved 007000 h fmcs [r/w] 1110x000 ________ ________ ________ flash memory control register 007004 h fmwt [r/w] --000011 ________ ________ ________ 007008 h | 00fffc h ________ reserved 010000 h | 010ffc h ________ reserved 011000 h | 011ffc h ________ i-ram 4 kb address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 51 10-apr-01 012000 h | 01fffc h ________ reserved 020000 h | 03bffc h ________ reserved 03c000 h | 03fffc h user ram 16 kb (d-bus) 040000 h | 043ffc h fast ram 16 kb (f-bus) 044000 h | 0feffc ________ reserved 050000 h | 0507fc h boot rom 2 kb (f-bus) 050800 h | 07fff4 h ________ reserved 080000 h | 09fffc h sector 0 64 kb sector 7 64 kb flash memory 512 k on f-bus 0a0000 h | 0bfffc sector 1 64 kb sector 8 64 kb 0c0000 h | 0dfffc sector 2 64 kb sector 9 64 kb 0e0000 h | 0efffc sector 3 32 kb sector 10 32 kb 0f0000 h | 0f3ffc h sector 4 8 kb sector 11 8 kb 0f4000 h | 0f7ffc h sector 5 8 kb sector 12 8 kb 0f8000 h | 0ffff4 h sector 6 16 kb sector 13 16 kb address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 52 10-apr-01 0ffff8 h fmv [r] 06 00 00 00 h fixed reset/mode vector 0ffffc h frv [r] 00 05 00 00 h write operations to address 0ffff8 h and 0ffffc h are not possible. when reading these addresses, the val- ues shown above will be read. address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 53 10-apr-01 100000 h bvalr0 [r/w] 00000000 00000000 treqr0 [r/w] 00000000 00000000 can 0 remark: address range for can 0 to can 1 depends on chip select range. men- tioned addresses are default val- ues, deter- mined by boot rom con- tents. 100004 h tcanr0 [w] 00000000 00000000 tcr0 [r/w] 00000000 00000000 100008 h rcr0 [r/w] 00000000 00000000 rrtrr0 [r/w] 00000000 00000000 10000c h rovrr0 [r/w] 00000000 00000000 rier0 [r/w] 00000000 00000000 100010 h csr0 [r/w] 00000000 00000001 leir0 [r/w] 000-0000 100014 h rtec0 [r] 00000000 00000000 btr0 [r/w] -1111111 11111111 100018 h ider0 [r/w] xxxxxxxx xxxxxxxx trtrr0 [r/w] 00000000 00000000 10001c h rfwtr0 [r/w] xxxxxxxx xxxxxxxx tier0 [r/w] 00000000 00000000 100020 h amsr0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100024 h amr00 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100028 h amr10 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 10002c h | 100048 h general purpose ram [r/w] 10004c h idr00 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100050 h idr10 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100054 h idr20 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100058 h idr30 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 10005c h idr40 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100060 h idr50 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100064 h idr60 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 54 10-apr-01 100068 h idr70 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx can 0 10006c h idr80 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100070 h idr90 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100074 h idr100 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100078 h idr110 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 10007c h idr120 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100080 h idr130 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100084 h idr140 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100088 h idr150 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 10008c h dlcr00 [r/w] -------- ----xxxx dlcr10 [r/w] -------- ----xxxx 100090 h dlcr20 [r/w] -------- ----xxxx dlcr30 [r/w] -------- ----xxxx 100094 h dlcr40 [r/w] -------- ----xxxx dlcr50 [r/w] -------- ----xxxx 100098 h dlcr60 [r/w] -------- ----xxxx dlcr70 [r/w] -------- ----xxxx 10009c h dlcr80 [r/w] -------- ----xxxx dlcr90 [r/w] -------- ----xxxx 1000a0 h dlcr100 [r/w] -------- ----xxxx dlcr110 [r/w] -------- ----xxxx 1000a4 h dlcr120 [r/w] -------- ----xxxx dlcr130 [r/w] -------- ----xxxx 1000a8 h dlcr140 [r/w] -------- ----xxxx dlcr150 [r/w] -------- ----xxxx 1000ac h dtr00 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000b4 h dtr10 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 55 10-apr-01 1000bc h dtr20 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 0 1000c4 h dtr30 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000cc h dtr40 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000d4 h dtr50 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000dc h dtr60 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000e4 h dtr70 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000ec h dtr80 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000f4 h dtr90 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000fc h dtr100 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100104 h dtr110 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10010c h dtr120 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100114 h dtr130 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10011c h dtr140 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100124 h dtr150 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10012c h creg0 [r/w] 00000000 00000110 address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 56 10-apr-01 100200 h bvalr1 [r/w] 00000000 00000000 treqr1 [r/w] 00000000 00000000 can 1 remark: address range for can 0 to can 1 depends on chip select range. men- tioned addresses are default val- ues, deter- mined by boot rom con- tents. 100204 h tcanr1 [w] 00000000 00000000 tcr1 [r/w] 00000000 00000000 100208 h rcr1 [r/w] 00000000 00000000 rrtrr1 [r/w] 00000000 00000000 10020c h rovrr1 [r/w] 00000000 00000000 rier1 [r/w] 00000000 00000000 100210 h csr1 [r/w] 00000000 00000001 leir1 [r/w] 000-0000 100214 h rtec1 [r] 00000000 00000000 btr1 [r/w] -1111111 11111111 100218 h ider1 [r/w] xxxxxxxx xxxxxxxx trtrr1 [r/w] 00000000 00000000 10021c h rfwtr1 [r/w] xxxxxxxx xxxxxxxx tier1 [r/w] 00000000 00000000 100220 h amsr1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100224 h amr01 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100228 h amr11 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 10022c h | 100248 h general purpose ram [r/w] 10024c h idr01 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100250 h idr11 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100254 h idr21[r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100258 h idr31 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx- 10025c h idr41 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100260 h idr51 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100264 h idr61 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 57 10-apr-01 100268 h idr71 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx can 1 10026c h idr81 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100270 h idr91 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100274 h idr101 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100278 h idr111 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 10027c h idr121 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxx--- 100280 h idr131 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100284 h idr141 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 100288 h idr151 [r/w] xxxxxxxx xxxxxxxx xxxxx--- xxxxxxxx 10028c h dlcr01 [r/w] -------- ----xxxx dlcr11 [r/w] -------- ----xxxx 100290 h dlcr21 [r/w] -------- ----xxxx dlcr31 [r/w] -------- ----xxxx 100294 h dlcr41 [r/w] -------- ----xxxx dlcr51 [r/w] -------- ----xxxx 100298 h dlcr61 [r/w] -------- ----xxxx dlcr71 [r/w] -------- ----xxxx 10029c h dlcr81[r/w] -------- ----xxxx dlcr91 [r/w] -------- ----xxxx 1002a0 h dlcr101 [r/w] -------- ----xxxx dlcr111 [r/w] -------- ----xxxx 1002a4 h dlcr121 [r/w] -------- ----xxxx dlcr131 [r/w] -------- ----xxxx 1002a8 h dlcr141 [r/w] -------- ----xxxx dlcr151 [r/w] -------- ----xxxx 1002ac h dtr01 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002b4 h dtr11 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 58 10-apr-01 1002bc h dtr21 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 1 1002c4 h dtr31 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002cc h dtr41 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002d4 h dtr51 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002dc h dtr61 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002e4 h dtr71 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002ec h dtr81 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002f4 h dtr91 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002fc h dtr101 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100304 h dtr111 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10030c h dtr121 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100314 h dtr131 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10031c h dtr141 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100324 h dtr151 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10032c h creg1 [r/w] 00000000 00000110 address register block +0 +1 +2 +3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 59 10-apr-01 appendix b interrupt vectors this appendix lists the interrupt vector table. the interrupt vector table lists the interrupt vectors and interrupt control registers assigned to each mb91360 interrupt. interrupt interrupt number interrupt level *1 interrupt vector *2 decimal hexa- decimal setting register register address offset default vector address rn reset *6 0 00 - - 0x3fc 0x000ffffc mode vector *6 1 01 - - 0x3f8 0x000ffff8 system reserved 2 02 - - 0x3f4 0x000ffff4 system reserved 3 03 - - 0x3f0 0x000ffff0 system reserved 4 04 - - 0x3ec 0x000fffec system reserved 5 05 - - 0x3e8 0x000fffe8 system reserved 6 06 - - 0x3e4 0x000fffe4 co-processor fault trap *4 7 07 - - 0x3e0 0x000fffe0 co-processor error trap *4 8 08 - - 0x3dc 0x000fffdc inte instruction *4 9 09 - - 0x3d8 0x000fffd8 instruction break exception *4 10 0a - - 0x3d4 0x000fffd4 operand break trap *4 11 0b - - 0x3d0 0x000fffd0 step trace trap *4 12 0c - - 0x3cc 0x000fffcc nmi interrupt(tool) *4 13 0d - - 0x3c8 0x000fffc8 undefined instruction exception 14 0e - - 0x3c4 0x000fffc4 nmi request 15 0f f h fixed 0x3c0 0x000fffc0 external interrupt 0 16 10 icr00 0x440 0x3bc 0x000fffbc 4 external interrupt 1 17 11 icr01 0x441 0x3b8 0x000fffb8 5 external interrupt 2 18 12 icr02 0x442 0x3b4 0x000fffb4 8 external interrupt 3 19 13 icr03 0x443 0x3b0 0x000fffb0 9 external interrupt 4 20 14 icr04 0x444 0x3ac 0x000fffac external interrupt 5 21 15 icr05 0x445 0x3a8 0x000fffa8 external interrupt 6 22 16 icr06 0x446 0x3a4 0x000fffa4
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 60 10-apr-01 external interrupt 7 23 17 icr07 0x447 0x3a0 0x000fffa0 reload timer 0 24 18 icr08 0x448 0x39c 0x000fff9c 6 reload timer 1 25 19 icr09 0x449 0x398 0x000fff98 7 reload timer 2 26 1a icr10 0x44a 0x394 0x000fff94 can 0 rx 27 1b icr11 0x44b 0x390 0x000fff90 can 0 tx/ns 28 1c icr12 0x44c 0x38c 0x000fff8c can 1 rx 29 1d icr13 0x44d 0x388 0x000fff88 can 1 tx/ns 30 1e icr14 0x44e 0x384 0x000fff84 can 2 rx 7 31 1f icr15 0x44f 0x380 0x000fff80 can 2 tx/ns 7 32 20 icr16 0x450 0x37c 0x000fff7c can 3 rx 5 33 21 icr17 0x451 0x378 0x000fff78 can 3 tx/ns 5 34 22 icr18 0x452 0x374 0x000fff74 ppg 0/1 35 23 icr19 0x453 0x370 0x000fff70 ppg 2/3 36 24 icr20 0x454 0x36c 0x000fff6c ppg 4/5 7 37 25 icr21 0x455 0x368 0x000fff68 ppg 6/7 7 38 26 icr22 0x456 0x364 0x000fff64 reload timer 3 7 39 27 icr23 0x457 0x360 0x000fff60 reload timer 4 7 40 28 icr24 0x458 0x35c 0x000fff5c reload timer 5 7 41 29 icr25 0x459 0x358 0x000fff58 icu 0/1 42 2a icr26 0x45a 0x354 0x000fff54 ocu 0/1 43 2b icr27 0x45b 0x350 0x000fff50 icu 2/3 44 2c icr28 0x45c 0x34c 0x000fff4c ocu 2/3 7 45 2d icr29 0x45d 0x348 0x000fff48 adc 46 2e icr30 0x45e 0x344 0x000fff44 14 timebase overflow 47 2f icr31 0x45f 0x340 0x000fff40 free running counter 0 48 30 icr32 0x460 0x33c 0x000fff3c free running counter 1 49 31 icr33 0x461 0x338 0x000fff38 sio 0 50 32 icr34 0x462 0x334 0x000fff34 sio 1 51 33 icr35 0x463 0x330 0x000fff30 sound generator 7 52 34 icr36 0x464 0x32c 0x000fff2c uart 0 rx 53 35 icr37 0x465 0x328 0x000fff28 0 uart 0 tx 54 36 icr38 0x466 0x324 0x000fff24 1 uart 1 rx 7 55 37 icr39 0x467 0x320 0x000fff20 2 uart 1 tx 7 56 38 icr40 0x468 0x31c 0x000fff1c 3
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 61 10-apr-01 *1 the icrs are located in the interrupt controller and set the interrupt level for each interrupt request. an icr is provided for each interrupt request. *2 the vector address for each eit (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (tbr). the tbr specifies the top of the eit vector table. the addresses listed in the table are for the default tbr value (0x000ffc00). the tbr is initialized to this value by a reset.after execution of the inter- nal boot rom tbr is set to 0 x 00ffc00. *3 used by realos *4 system reserved *5 only available on mb91v360/mb91fv360 *6 mode and reset vector cannot be changed, for their contents see io map *7 not available on MB91F367Ga/f368ga uart 2 rx 7 57 39 icr41 0x469 0x318 0x000fff18 10 uart 2 tx 7 58 3a icr42 0x46a 0x314 0x000fff14 11 i2c 59 3b icr43 0x46b 0x310 0x000fff10 13 alarm comparator 60 3c icr44 0x46c 0x30c 0x000fff0c rtc / calibration 8 (watchtimer) 61 3d icr45 0x46d 0x308 0x000fff08 dma 62 3e icr46 0x46e 0x304 0x000fff04 delayed interrupt activation bit 63 3f icr47 0x46f 0x300 0x000fff00 system reserved *3 64 40 - - 0x2fc 0x000ffefc system reserved *3 65 41 - - 0x2f8 0x000ffef8 security vector 66 42 0x2f4 0x000ffef4 system reserved 67 43 (icr51) 0x473 0x2f0 0x000ffef0 system reserved 68 44 (icr52) 0x474 0x2ec 0x000ffeec system reserved 69 45 (icr53) 0x475 0x2e8 0x000ffee8 system reserved 70 46 (icr54) 0x476 0x2e4 0x000ffee4 system reserved 71 47 (icr55) 0x477 0x2e0 0x000ffee0 system reserved 72 48 (icr56) 0x478 0x2dc 0x000ffedc system reserved 73 49 (icr57) 0x479 0x2d8 0x000ffed8 system reserved 74 4a (icr58) 0x47a 0x2d4 0x000ffed4 system reserved 75 4b (icr59) 0x47b 0x2d0 0x000ffed0 system reserved 76 4c (icr60) 0x47c 0x2cc 0x000ffecc system reserved 77 4d (icr61) 0x47d 0x2c8 0x000ffec8 system reserved 78 4e (icr62) 0x47e 0x2c4 0x000ffec4 system reserved 79 4f (icr63) 0x47f 0x2c0 0x000ffec0 used by the int instruction. 80 to 255 50 to ff -- 0x2bc to 0x000 0x000ffebc to 0x000ffc00
fme / emdc / br+jr - MB91F367G_f368g_ds.fm 62 10-apr-01 *8 calibration unit is not available on f365g remarks: the 1-kbyte area from the address specified in tbr is the eit vector area. each vector consists of four bytes. the following formula shows the relationship between the vector number and vector address. vctadr=tbr + vctofs =tbr + (3fc h C 4 vct) vctadr:vector address vctofs:vector offset vct:vector number

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